Advanced Computer Architecture I

CECS 530- Advanced Computer Architecture I

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Textbook

Computer Architecture: A Quantitative Approach
Hennessy & Patterson, 3rd Edition
Morgan-Kauffman, 2003
ISBN: 1558605967

References:

1. “Computer Organization and Design”, Hennessy and Patterson, 3rd edition, Morgan Kaufmann, 2004
2. “Logic and Computer Design Fundamentals”, Mano & Kime, 2nd Edition updated, Prentice Hall, 2001

Learning Objectives (Learning Outcomes Expected):

We will learn some of the techniques used to improve the performance of computers – Parallelism in Instruction level – Hardware approaches - pipelining, dynamic scheduling, superscalar processors, multiple issue of instructions. We may also learn some of the Software approaches. Multiprocessing, interconnection networks and clusters are also used to improve the performance of computers. Memory hierarchy is another technique for speed-up. These topics will be covered in a follow-up course.

Course Overview (The Big Picture - The Bird's Eye View)

The course has two components - Theory and Laboratory.

Theory:

In the theory segment, we talk about the history of computer architecture and the different components in Computer Design. We review Instruction Set Architecture, review Design of Data Path and Design of Control Unit. One of the key mechanisms used to improve the performance of computers is to introduce Parallelism – either at the single instruction level or at the multiple instruction level (program level). One of the instruction level parallelisms (ILP) is Pipelining. We study pipelining, the hazards we face in pipelining and their solutions. We then study about dynamic scheduling techniques – Scoreboarding and Tomasulo’s algorithm. We discuss multiple execution units and multiple issue of instructions and problems encountered. We then talk about software approaches - parallelizing the code by compiler. We touch on vector processors (Single Instruction Multiple Data Stream (SIMD) processors).

A follow-up course will cover the following: study of multiprocessors, how memory can be shared between them, how we can keep the memory consistent and how we can synchronize the operations between processors. The next topic is interconnection of computers at various levels – locally, in wider area and then globally. We discuss clusters used for data bases and web servers. We then move on to Memory hierarchy which is another technique used to speed up processors and discuss the various issues arising in the hierarchy.

Laboratory:

In the Lab, we model and simulate the pipelined architecture we study in theory. We start by simulating a simple non-pipelined computer. Obviously we cannot begin with a big computer. We use a small subset of the commercial MIPS computer. We build brick by brick incrementally. We take “baby steps”. At each step, we test the entity, build another entity, test it and then integrate the two entities and test the bigger entity etc. Then we introduce pipelining to the simple non-pipelined computer and study hazards and their solutions.

The Hardware Description Language (HDL) that we use to describe the hardware in the Lab is VHDL. V stands for VHSIC (Very High Speed Integrated Circuits). VHDL simulator called ‘nclaunch’ is part of the different design tools provided by Cadence in our labs. The Cadence server runs on Sun workstations and we access it through Linux clients in the lab. We invoke x windows and open many windows to create and edit VHDL files and to telnet to Cadence. The first Lab will make us familiar with these tools.